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CXG1109EN
Receive Dual Low Noise Amplifier/Mixer
Description The CXG1109EN is a receive dual low noise amplifier/ mixer MMIC. This IC is designed using the Sony's GaAs J-FET process. Features * High conversion gain: Gp = 16.5 to 17dB (LNA Typ.) Gc = 9.5 to 10dB (MIX Typ.) * Low noise figure: NF = 1.5dB (LNA Typ.) NF = 4 to 5dB (MIX Typ.) * Single 3V power supply operation * Low LO input power operation PLO = -12.5dBm * Single CTL pin achieved by the built-in inverter circuit * 16-pin VSON package Applications 800MHz Japan digital cellular telephones (PDC) Structure GaAs J-FET MMIC 16 pin VSON (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD 4.5 V * Input power PIN +13 dBm * Current consumption IDD 15 mA * Operating temperature Topr -35 to +85 C * Storage temperature Tstg -65 to +150 C Recommended Operating Voltages 2.7 to 3.3 * Supply voltage VDD * Control voltage VCTL (H) 2.4 to 3.3 VCTL (L) 0 to 0.3
V V V
Block Diagram
Pin Configuration
LNA RFIN1
9
8
LNA RFIN2
LNA RFIN1
9
8 7 6 5 4 3 2 1
LNA RFIN2 CAP LNA RFOUT/VDD1 (LNA) GND OPT MIX RFIN GND LO IN
CAP 10
6 LNA RFOUT
GND 11 CTL 12 GND 13
3
MIX RFIN
GND 14 VDD2 (LO AMP) 15
IFOUT 16
1
LO IN
IFOUT/VDD3 (MIX) 16
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E00924A1Y-PS
CXG1109EN
Electrical Characteristics Conditions: VDD = 3.0V, VCTL (H) = 3.0V, VCTL (L) = 0V, fRF1 = 885MHz, fRF2 = 810MHz, fLO = fRF - 130MHz, PLO = -12.5dBm, Ta = 25C, unless otherwise specified Low Noise Amplifier Block Item Current consumption Control current Symbol IDD ICTL Path -- -- RFIN1 RFOUT Power gain Gp RFIN2 RFOUT Noise figure Input IP3 Isolation NF IIP3 ISO RFIN1 RFOUT RFIN2 RFOUT RFIN1 RFOUT RFIN2 RFOUT RFOUT RFIN1 RFOUT RFIN2 fRF2 fRF1 fRF2 fRF1 fRF2 fRF1 fRF2 RF frequency VCTL Min. Typ. Max. Unit -- -- -- -- fRF1 H L H L H L H L H L H L H L -- -- -- -1 15 -- -- 15 -- -- 1.9 1.9 55 0 16.5 2.5 2.5 80 -- 19 dB When a small signal dB dBm 1 dB When a small signal mA When no signal A Measurement condition
-20 -15 -26 -21 17 1.5 1.5 19 2 2 -- -- -- --
-11 -7.5 -12.5 -9 17 18 22 23
Mixer Block Item Current consumption Power gain Noise figure Input IP3 LO to RF leak level Symbol IDD GC NF IIP3 Plk RF frequency -- fRF1 fRF2 fRF1 fRF2 fRF1 fRF2 fRF1 fRF2 Min. -- 9 8.5 -- -- -1 -1.5 -- -- Typ. 4.5 10 9.5 5 4 1.5 1.5 -22 -24 Max. 6.2 11.5 11 6.5 5.5 -- -- -17 -19 Unit mA dB When a small signal dB dBm 1 dBm fLO = 755MHz fLO = 680MHz Measurement condition When no signal
The values shown above are the specified values on the Sony's recommended evaluation board. 1 Conversion from the IM3 suppression ratio for two-wave input: PRF = -30dBm (low noise amplifier block)/ -22.5dBm (mixer block) at fRFoffset = 100kHz.
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CXG1109EN
Recommended Evaluation Circuit
LNA RFIN1 50 LNA RFIN2 50 LNA RFOUT 50 L12 13 L3 VDD2 (LO AMP) C5 IFOUT 50 VDD3 (MIX) C3 50 C4 15 C2 L2 L1 C1 16 2 1 L7 14 3 R1 L8 4 C7 L9 L10 LOIN 50 VDD1 (LNA) MIX RFIN
L5 L6
L4 9 C6 10 11 7 C9 6 5 8
L13
L14 L15
L11 C10
C8
CTL
12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10
220nH 220nH 33nH 18nH 6.8nH 27nH 39nH 22nH 1.2nH 8.2nH
L11 L12 L13 L14 L15 C1 C2 C3 C4 C5
18nH 12nH 22nH 5.6nH 27nH 5pF 1000pF 1000pF 100pF 1000pF
C6 C7 C8 C9 C10 R1
18pF 1000pF 100pF 47pF 1000pF 680
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CXG1109EN
Example of Representative Characteristics (Ta = 25C) Low Noise Amplifier Block
Gp, NF vs. fRF
18 17.5 17
Gp - Power gain [dB]
Gp, NF vs. fRF
3 18 17.5 2.5 17
Gp - Power gain [dB]
3 VDD = 3V VCTL = 0V Gp 2.5
VDD = 3V VCTL = 3V
Gp
NF - Noise figure [dB]
16.5 16 15.5 15 14.5 1 14 800 810 820 830 840 850 860 870 880 890 900 fRF - RF frequency [MHz] NF 1.5 2
16.5 16 15.5 15 NF 14.5 1 14 800 810 820 830 840 850 860 870 880 890 900 fRF - RF frequency [MHz] 1.5 2
POUT, IM3 vs. PIN
20 10 0
POUT - RF output power [dBm] POUT - RF output power [dBm]
POUT, IM3 vs. PIN
20 10 0
-10 -20 -30 -40 -50 -60 -70
POUT
-10 -20 -30 -40 -50 -60 -70
POUT
IM3
IM3
VDD = 3V VCTL = 3V fRF1 = 885MHz fRF2 = 885.1MHz
VDD = 3V VCTL = 0V fRF1 = 810MHz fRF2 = 810.1MHz
-80 -40 -35 -30 -25 -20 -15 -10 -5 0 PIN - RF input power [dBm]
5 10
-80 -40 -35 -30 -25 -20 -15 -10 -5 0 PIN - RF input power [dBm]
5 10
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NF - Noise figure [dB]
CXG1109EN
Mixer Block
Gc, NF vs. fRF
12 Gc 11 7
Gc - Conversion gain [dB]
9 8 7 6 NF 5 3 4 800 810 820 830 840 850 860 870 880 890 900 fRF - RF frequency [MHz] 4 VDD = 3V fLO = fRF - 130MHz PLO = -12.5dBm 5
POUT, IM3 vs. PIN
20 10 0 20 10 0
NF - Noise figure [dB]
10
6
POUT, IM3 vs. PIN
POUT - IF output power [dBm]
-20 -30 -40 -50 -60 -70 -80 -40 -35 -30 -25 -20 -15-10 -5 0 5 10 IM3 VDD = 3V fRF1 = 885MHz fRF2 = 885.1MHz fLO = 755MHz
POUT - IF output power [dBm]
-10
POUT
POUT -10 -20 -30 -40 -50 -60 -70 -80 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 VDD = 3V fRF1 = 810MHz fRF2 = 810.1MHz fLO = 680MHz IM3
PIN - RF input power [dBm]
PIN - RF input power [dBm]
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CXG1109EN
IIP3, PLK vs. PLO
3 2.5 -10 3 2.5
IIP3, PLK vs. PLO
-10
PLK - LO leak power [dBm]
IIP3 - Input power [dBm]
IIP3 - Input power [dBm]
2 1.5 1 PLK 0.5 0 -0.5 -1 -25 VDD = 3V fRF1 = 885MHz fRF2 = 885.1MHz fLO = 755MHz -20 -15 -10 -5 0
-15
2 1.5 1 0.5 0 -0.5
IIP3
-15
-20
-20
-25
PLK VDD = 3V fRF1 = 810MHz fRF2 = 810.1MHz fLO = 680MHz -20 -15 -10 -5 0
-25
-30
-1 -25
-30
PLO - LO input power [dBm]
PLO - LO input power [dBm]
Gc, NF vs. PLO
16 14 10 9 16 14
Gc, NF vs. PLO
10 VDD = 3V fRF1 = 810MHz fRF2 = 810.1MHz fLO = 680MHz Gc 10 8 6 4 2 0 -25 NF 7 6 5 4 3 2 -20 -15 -10 -5 0 PLO - LO input power [dBm] 9
Gc - Conversion gain [dB]
NF - Noise figure [dB]
10 8 6 4 2 0 -25 NF VDD = 3V fRF1 = 885MHz fRF2 = 885.1MHz fLO = 755MHz -20 -15 -10 -5 0
7 6 5 4 3 2 PLO - LO input power [dBm]
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NF - Noise figure [dB]
12
Gc
8
Gc - Conversion gain [dB]
12
8
PLK - LO leak power [dBm]
IIP3
CXG1109EN
Example of Characteristics for Option Resistance R1 Changed (Ta = 25C)
IDD3 - Mixer block current consumption (MIX) [mA]
IDD3 (MIX) vs. R1
8 VDD = 3V 7 6 5 4 3 2 1 0 OPEN 1200 820 680
470 390 270 220 150
R1 - Option resistance []
GC, NF vs. R1
12 GC 10
GC - Conversion gain, NR-Noise figure [dB] GC - Conversion gain, NF-Noise figure [dB]
GC, NF vs. R1
12 GC 10
8
6 NF 4
VDD = 3V fRF = 885MHz fLO = 755MHz PLO = -12.5dBm
8
6 NF
VDD = 3V fRF = 810MHz fLO = 680MHz PLO = -12.5dBm
4
2 OPEN 1200 820 680
470 390 270 220 150
2 OPEN 1200 820 680
470 390 270 220 150
R1 - Option resistance []
R1 - Option resistance []
IIP3, PLK vs. R1
4 3.5 3 2.5 2 IIP3 1.5 1 0.5 0 OPEN 1200 820 680 VDD = 3V fRF = 885MHz fLO = 755MHz PLO = -12.5dBm PLK -20 -21
PLK - LO leak power [dBm]
IIP3, PLK vs. R1
4 3.5
IIP3 - Input IP3 [dBm]
-20 -21 -22 -23 IIP3 -24 -25 PLK VDD = 3V fRF = 810MHz fLO = 680MHz PLO = -12.5dBm -26 -27
PLK - LO leak power [dBm]
IIP3 - Input IP3 [dBm]
-22 -23 -24 -25 -26 -27
3 2.5 2 1.5 1 0.5 0 OPEN 1200 820 680
-28 470 390 270 220 150
-28 470 390 270 220 150
R1 - Option resistance []
R1 - Option resistance []
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CXG1109EN
Recommended Evaluation Board Front
50mm
LNA RFIN1
LNA RFIN2
50mm
IFOUT
LNA RFOUT
LO IN
MIX RFIN
CTL
VDD2
GND
VDD3
VDD1
Glass fabric-base 4-layer epoxy board (thickness: 0.2mm x 2) GND for the whole 2nd and 3rd layers
Enlarged Diagram of Center Part
L6 L14 L5 L4 C6 L15 L13 C9 L11 C10 C5 C4 L3 R1 L8 C1 L1 L7 L9 L10 C7 L12 C8
L2 C2
C3
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CXG1109EN
Package Outline
Unit: mm
16PIN VSON (PLASTIC)
0.9 MAX 0.6 3.5 A S
0.35 0.1 2.5
0.05 S
B 0.4 1.4 4x
2x 0.2 S B 0.35 0.1
0.2 S A B
0.23 0.02 0.35 0.1 2.5 0.23 0.02 0.5 0.2
0.05 M S A-B
0.03 0.03 0.2 0.01
Soldrer Plating 0.13 0.025 + 0.09 0.14 - 0.03 NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VSON-16P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02 g
Kokubu Ass'y
16PIN VSON (PLASTIC)
0.9 MAX 0.6 3.5 A S 0.05 S
B 0.4 1.4 4x
2.7
2x 0.2 S B 0.35 0.1
0.2 S A B 0.05 M S A-B
0.03 0.03 0.2 0.01
Soldrer Plating 0.13 0.025 + 0.09 0.14 - 0.03 NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VSON-16P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02 g
LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m
0.5 0.2
2.7
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Sony Corporation

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